A block of digital logic that is designed to be implemented in an ASIC or FPGA chip. A soft core is typically delivered in RTL, which is a hardware description language that defines logic at a higher level than a "hard core," which is at the gate level. A chip design may comprise one or more soft cores combined with one or more hard cores along with other blocks of user-defined logic. Occasionally, soft cores are delivered as gate-level netlists or schematics rather than RTL.
Soft Cores in ASICs
For ASIC chips, the RTL soft core and other RTL associated with the design are synthesized into a gate-level netlist. Based on the netlist, the logic gates are placed and routed and then turned into photomasks to make the chip. The ultimate realization of the soft core is hardwired logic gates formed of transistors and their interconnections.
Soft Cores in FPGAs
With FPGAs, the resulting netlist is used to generate a configuration file that will be used to program the lookup tables and configurable logic blocks inside the device. See core, hard core, netlist, ASIC and FPGA.
How Soft Cores Fit In
Soft cores delivered in RTL are the first stage of circuit development. This chart illustrates an ASIC chip. With FPGAs, the microprocessor core and other IP blocks are already in place. Consequently, instead of a gate-level netlist, a lookup table/configurable logic block (LUT/CLB) netlist is created, and the final output for FPGAs is a configuration file rather than GDSII files.
Soft Cores in ASICs
For ASIC chips, the RTL soft core and other RTL associated with the design are synthesized into a gate-level netlist. Based on the netlist, the logic gates are placed and routed and then turned into photomasks to make the chip. The ultimate realization of the soft core is hardwired logic gates formed of transistors and their interconnections.
Soft Cores in FPGAs
With FPGAs, the resulting netlist is used to generate a configuration file that will be used to program the lookup tables and configurable logic blocks inside the device. See core, hard core, netlist, ASIC and FPGA.
How Soft Cores Fit In
Soft cores delivered in RTL are the first stage of circuit development. This chart illustrates an ASIC chip. With FPGAs, the microprocessor core and other IP blocks are already in place. Consequently, instead of a gate-level netlist, a lookup table/configurable logic block (LUT/CLB) netlist is created, and the final output for FPGAs is a configuration file rather than GDSII files.
 | Reproduced with permission from Computer Desktop Encyclopedia. Copyright (c) 1981-2009 The Computer Language Company Inc. All rights reserved. |
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