The CPU family from Intel that is based on its next-generation, 64-bit IA-64 architecture. The operating systems that are available for Itanium computers are Windows Server 2003, HP-UX and Linux.
Itaniums run IA-64 applications in the CPU's native mode, and they run IA-32 (x86) and HP PA-RISC applications in an emulation mode. IA-32 programs are executed directly in the Itanium's hardware layer or via a software layer in the operating system (see IA-32 Execution Layer). HP PA-RISC applications are run via a software translator (see Aries).
Following are the various Itanium models that have been released along with their code names (in parentheses) as well as models expected in the future. See IA-64 for more on the Itanium architecture.
First Itanium (Merced)
The first Itanium chips were introduced in 2001 with a clock speed of 733 MHz and a 180 nanometer process technology. L3 cache sizes were up to 4MB.
Itanium 2 (McKinley, Madison, Deerfield, Fanwood)
Starting in 2002, the Itanium 2 line was released with clock speeds starting at 900 MHz and increasing to 1.7 GHz. Memory bandwidth was increased from the first Itanium's 2.1 Gbps to 6.4 Gbps. Starting with the Madison chips in 2003, the process technology was reduced to 130 nanometers. L3 cache sizes reached 9MB.
Dual Core Itanium 2 (Montecito, Millington)
In 2006, the third generation Itanium models were introduced with dual cores, up to 24MB L3 cache and 1.7 billion transistors.
Itanium 3? (Tukwila, Poulson, Kittson)
Quad-core Itaniums, code named Tukwila, are expected in 2008 with a process technology of 65 nm. Poulson and Kittson are future chips with more cores.
Itaniums run IA-64 applications in the CPU's native mode, and they run IA-32 (x86) and HP PA-RISC applications in an emulation mode. IA-32 programs are executed directly in the Itanium's hardware layer or via a software layer in the operating system (see IA-32 Execution Layer). HP PA-RISC applications are run via a software translator (see Aries).
Following are the various Itanium models that have been released along with their code names (in parentheses) as well as models expected in the future. See IA-64 for more on the Itanium architecture.
First Itanium (Merced)
The first Itanium chips were introduced in 2001 with a clock speed of 733 MHz and a 180 nanometer process technology. L3 cache sizes were up to 4MB.
Itanium 2 (McKinley, Madison, Deerfield, Fanwood)
Starting in 2002, the Itanium 2 line was released with clock speeds starting at 900 MHz and increasing to 1.7 GHz. Memory bandwidth was increased from the first Itanium's 2.1 Gbps to 6.4 Gbps. Starting with the Madison chips in 2003, the process technology was reduced to 130 nanometers. L3 cache sizes reached 9MB.
Dual Core Itanium 2 (Montecito, Millington)
In 2006, the third generation Itanium models were introduced with dual cores, up to 24MB L3 cache and 1.7 billion transistors.
Itanium 3? (Tukwila, Poulson, Kittson)
Quad-core Itaniums, code named Tukwila, are expected in 2008 with a process technology of 65 nm. Poulson and Kittson are future chips with more cores.
 | Reproduced with permission from Computer Desktop Encyclopedia. Copyright (c) 1981-2008 The Computer Language Company Inc. All rights reserved. |
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