A block of digital logic that is designed to be implemented in an ASIC or FPGA chip. A chip design may be made up of one or more hard cores combined with one or more soft cores along with other blocks of user-defined logic.
For ASIC chips, a hard core is delivered as logic gates in which their physical locations relative to each other and their interconnections are predefined. This block will be treated as a "black box" by the place-and-route software that processes the entire design. The location of the block as a whole may be determined by the software, but the block's internal contents are "locked down."
With FPGAs, hard cores are already physically implemented as hardwired blocks embedded into the FPGA's fabric. See core, soft core, ASIC and FPGA.
How Hard Cores Fit In
When used in an ASIC chip, information about the hard core is entered at various stages to make room for it before its actual layers are added. With FPGAs, floor planning is still done, but the microprocessor core and other IP blocks are already in place. Consequently, instead of a gate-level netlist, a lookup table/configurable logic block (LUT/CLB) netlist is created, and the final output for FPGAs is a configuration file rather than GDSII files.
For ASIC chips, a hard core is delivered as logic gates in which their physical locations relative to each other and their interconnections are predefined. This block will be treated as a "black box" by the place-and-route software that processes the entire design. The location of the block as a whole may be determined by the software, but the block's internal contents are "locked down."
With FPGAs, hard cores are already physically implemented as hardwired blocks embedded into the FPGA's fabric. See core, soft core, ASIC and FPGA.
How Hard Cores Fit In
When used in an ASIC chip, information about the hard core is entered at various stages to make room for it before its actual layers are added. With FPGAs, floor planning is still done, but the microprocessor core and other IP blocks are already in place. Consequently, instead of a gate-level netlist, a lookup table/configurable logic block (LUT/CLB) netlist is created, and the final output for FPGAs is a configuration file rather than GDSII files.
 | Reproduced with permission from Computer Desktop Encyclopedia. Copyright (c) 1981-2009 The Computer Language Company Inc. All rights reserved. |
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