The gate array is made up of "basic cells," each cell containing some number of transistors and resistors depending on the vendor. Using a cell library (gates, registers, etc.) and a macro library (more complex functions), the customer designs the chip, and the vendor's software generates the interconnection masks. Some cells go wasted on gate array designs, which is the penalty for having fixed locations for everything. See PLD, ASIC, hard macro and soft macro.
Gate Array Cells
These are examples of basic cells used in gate arrays. One uses CMOS logic only (NMOS and PMOS transistors), while the other adds bipolar transistors for higher output power.
![]() | Reproduced with permission from Computer Desktop Encyclopedia. Copyright (c) 1981-2009 The Computer Language Company Inc. All rights reserved. |
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