A 64-core chip from Tilera Corporation, Santa Clara, CA (www.tilera.com). Introduced in 2007 and based on an architecture from MIT, the TILE64 was designed to run under a symmetric multiprocessing (SMP) version of Linux. The initial, target applications for the chip are special-purpose devices for networking and high-definition video (embedded system market).
Sixty-Four Cores and a Switch Fabric
The chip has 64 cores, each with its own L1 and L2 caches and a switch to connect it to the "iMesh" switch fabric (each core with its caches and switch is called a "tile"). The chip also contains controllers for memory, Ethernet, PCI Express and serial I/O. All tiles can access the caches of all the other tiles, providing a third cache layer before having to access main memory.
The TILE64 also comes with an Eclipse-based software development environment, which includes a C compiler, command line interfaces and simulation and profiling tools for multicore applications.
Impressive Specs for a Single Chip
At a clock rate of only 1 GHz, which keeps power requirements low, the chip provides 192 billion instructions per second, 27 Tbps of mesh interconnect and 50 Gbps of I/O bandwidth.
The TILE64
Along with its 8x8 grid of tiles, the TILE64 contains controllers for DDR2 memory, Ethernet, PCI Express and other I/O. Each tile (bottom) includes a core, caches and switch. (Image courtesy of Tilera Corporation, www.tilera.com)
Sixty-Four Cores and a Switch Fabric
The chip has 64 cores, each with its own L1 and L2 caches and a switch to connect it to the "iMesh" switch fabric (each core with its caches and switch is called a "tile"). The chip also contains controllers for memory, Ethernet, PCI Express and serial I/O. All tiles can access the caches of all the other tiles, providing a third cache layer before having to access main memory.
The TILE64 also comes with an Eclipse-based software development environment, which includes a C compiler, command line interfaces and simulation and profiling tools for multicore applications.
Impressive Specs for a Single Chip
At a clock rate of only 1 GHz, which keeps power requirements low, the chip provides 192 billion instructions per second, 27 Tbps of mesh interconnect and 50 Gbps of I/O bandwidth.
The TILE64
Along with its 8x8 grid of tiles, the TILE64 contains controllers for DDR2 memory, Ethernet, PCI Express and other I/O. Each tile (bottom) includes a core, caches and switch. (Image courtesy of Tilera Corporation, www.tilera.com)
 | Reproduced with permission from Computer Desktop Encyclopedia. Copyright (c) 1981-2008 The Computer Language Company Inc. All rights reserved. |
Additional Resources
- Processor geeks convene at Hot Chips 19
- News.com is covering the Hot Chips 19 conference on high performance processors taking place this week at Stanford University. Among the highlights, chip-to-chip interconnect technology; wireless HDTV transmission for home use; looking beyond CMOS to photonics, nanotech and quantum computing; the Tile64 chip from Tilera; science fiction icon Vernor Vinge...
- Blog posts 2007-08-21
- Is AMD's 65nm SOI process broken?
- Is AMD's 65nm SOI process broken?As soon as I read the headline...I knew it had to be George.Your bashing has become boring.Seems to be..and after all the SOI hubbub, too!Good topic. AMD made a huge stink about it's incredible and innovative SOI process a few years ago. That along...
- Discussion threads 2007-08-21
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