(Reduced Instruction Set Computer) A computer architecture that reduces chip complexity by using simpler instructions. RISC compilers have to generate software routines to perform complex instructions that were previously done in hardware by CISC computers. In RISC, the microcode layer and associated overhead is eliminated.
RISC keeps instruction size constant, bans the indirect addressing mode and retains only those instructions that can be overlapped and made to execute in one machine cycle or less. The RISC chip is faster than its CISC counterpart and is designed and built more economically.
RISC Vs. CISC
The RISC machine executes instructions faster because it does not have to go through a microcode conversion layer. The RISC compiler generates more instructions than the CISC compiler for the same processing.
RISC keeps instruction size constant, bans the indirect addressing mode and retains only those instructions that can be overlapped and made to execute in one machine cycle or less. The RISC chip is faster than its CISC counterpart and is designed and built more economically.
RISC Vs. CISC
The RISC machine executes instructions faster because it does not have to go through a microcode conversion layer. The RISC compiler generates more instructions than the CISC compiler for the same processing.
 | Reproduced with permission from Computer Desktop Encyclopedia. Copyright (c) 1981-2008 The Computer Language Company Inc. All rights reserved. |
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